/*******************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************/


#include "xparameters.h"
#include "xzdma.h"

/*
*@file xzdma.c
*@addtogroup zdma Overview
*
*
* The configuration table for devices
*/

XZDma_Config XZDma_ConfigTable[] = {
	{
		XPAR_PSU_ADMA_CH0_DEVICE_ID,
		XPAR_PSU_ADMA_CH0_BASEADDR,
		XPAR_PSU_ADMA_CH0_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH1_DEVICE_ID,
		XPAR_PSU_ADMA_CH1_BASEADDR,
		XPAR_PSU_ADMA_CH1_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH2_DEVICE_ID,
		XPAR_PSU_ADMA_CH2_BASEADDR,
		XPAR_PSU_ADMA_CH2_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH3_DEVICE_ID,
		XPAR_PSU_ADMA_CH3_BASEADDR,
		XPAR_PSU_ADMA_CH3_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH4_DEVICE_ID,
		XPAR_PSU_ADMA_CH4_BASEADDR,
		XPAR_PSU_ADMA_CH4_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH5_DEVICE_ID,
		XPAR_PSU_ADMA_CH5_BASEADDR,
		XPAR_PSU_ADMA_CH5_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH6_DEVICE_ID,
		XPAR_PSU_ADMA_CH6_BASEADDR,
		XPAR_PSU_ADMA_CH6_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH7_DEVICE_ID,
		XPAR_PSU_ADMA_CH7_BASEADDR,
		XPAR_PSU_ADMA_CH7_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH0_DEVICE_ID,
		XPAR_PSU_GDMA_CH0_BASEADDR,
		XPAR_PSU_GDMA_CH0_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH1_DEVICE_ID,
		XPAR_PSU_GDMA_CH1_BASEADDR,
		XPAR_PSU_GDMA_CH1_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH2_DEVICE_ID,
		XPAR_PSU_GDMA_CH2_BASEADDR,
		XPAR_PSU_GDMA_CH2_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH3_DEVICE_ID,
		XPAR_PSU_GDMA_CH3_BASEADDR,
		XPAR_PSU_GDMA_CH3_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH4_DEVICE_ID,
		XPAR_PSU_GDMA_CH4_BASEADDR,
		XPAR_PSU_GDMA_CH4_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH5_DEVICE_ID,
		XPAR_PSU_GDMA_CH5_BASEADDR,
		XPAR_PSU_GDMA_CH5_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH6_DEVICE_ID,
		XPAR_PSU_GDMA_CH6_BASEADDR,
		XPAR_PSU_GDMA_CH6_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH7_DEVICE_ID,
		XPAR_PSU_GDMA_CH7_BASEADDR,
		XPAR_PSU_GDMA_CH7_DMA_MODE
	}
};
